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rohs compliant - by exemption (see page 15) yellow IPD2131 high efficiency red ipd2132 high efficiency green ipd2133 0.200?? 8-character 5x7 dot matrix x-y stackable alphanumeric programmable display? 2006-04-04 1 description the IPD2131 (yellow), ipd2132 (high efficiency red) and ipd2133 (high efficiency green) are eight-digit high reliability 5 x 7 dot matrix programmable displays that are aimed at satisfying the most demanding display requirements. they are designed for use in extremely harsh environments where only the most reliable parts are acceptable. the devices are constructed in ceramic packages with eight 4.85 mm (0.200??) high 5 x 7 dot matrix digits. the devices incorporate the latest in cmos technology which is the heart of the device intelligence. the cmos ic is controlled by a user supplied eight-bit data word on a bidirectional bus. the ascii data and attribute data are word driven. this approach allows the displays to interface using similar techniques as a micro - processor peripheral. applications include: control panels, night viewing applica - tions, cockpit monitors, portable and vehicle technology as well as industrial controllers. esd warning: standard precautions for cmos handling should be observed. features eight 4.85 mm (0.200") dot matrix characters in a ceramic package true hermetic glass flat seal for all colors internal rom with 128 ascii characters internal ram for up to 16 user definable characters programmable control word allows user to select from 8 brightness levels, display blink, character flash, self test, or clear functions internal or external clock capability 8 bit bidirectional data bus allows for read/write capability contains all display drive and multiplexing circuitry reset pin for display initialization, multiple display blinking and flashing synchronization ttl compatible operating temperature range: ?55 to +100 c storage temperature: ?65 to +125 c categorized for luminous intensity and color x-y stackable
2006-04-04 2 IPD2131, ipd2132, ipd2133 package outlines dimensions in mm (inch) ordering information type color of emission character height mm (inch) ordering code IPD2131 yellow 4.85 (0.200) q68000a8904 ipd2132 high efficiency red q68000a8836 ipd2133 high efficiency green q68000a8906 idod5204 osram ipd213x yyww v z 2.7 (0.105) 5.3 (0.210) 2.8 (0.111) 42.7 (1.680) max. 42.4 (1.669) min. 0.8 (0.030) 4.8 (0.191) 4.9 (0.195) 1.1 (0.045) 9.9 (0.390) intensity code eia date code hue category 2.3 (0.090) typ. 2.54 (0.100) typ. non cum. 12.7 (0.500) 0.5 (0.020) typ. 1.3 (0.050) typ. 6.3 (0.250) max. 1.8 (0.070) typ. 6.0 (0.240) seating plane 5.3 (0.210) ref. 4.6 (0.180) 0.4 (0.015) typ. 7.6 (0.300) tolerance: 0.30 (0.015)
IPD2131, ipd2132, ipd2133 2006-04-04 3 maximum ratings ( t a =25 c) parameter symbol value unit operating temperature range t op ? 55 ? + 100 c storage temperature range t stg ? 65 ? + 125 c dc supply voltage, v cc to gnd (max. voltage with no leds on) v cc -0.3 to + 7.0 v input voltage levels, all inputs -0.3 to ( v cc + 0.3) v operating voltage, v cc to gnd (max. voltage with 20 dots/digits on) 5.5 v solder temperature 1.59 mm (0.063?) below seating plane, t < 5.0 s t s 260 c relative humidity (non-condensing) 85 % esd (100 pf, 1.5 k ? ), each pin v z 4.0 kv optical characteristics at 25 c ( v cc =5.0 v at 100% brightness level description symbol values unit yellow IPD2131 high efficiency red ipd2132 high efficiency green ipd2133 luminous intensity (min.) (typ.) i v 125 205 125 350 150 500 cd/dot cd/dot peak wavelength (typ.) peak 583 635 568 nm dominant wavelength (typ.) dom 585 626 574 nm notes: 1) i cc is an average value. 2) i cc is measured with the display at full brightness. peak i cc = 28 / 15 i cc average (#displayed).
IPD2131, ipd2132, ipd2133 2006-04-04 4 enlarged character font dimensions in inch (mm) maximum power dissipation vs. ambient temperature derating based on t j max=125 c idod5205 c1 c2 c3 c4 c5 r1 r2 r3 r4 r5 r6 r7 2.85 (0.112) 0.76 (0.030) typ. 0.65 (0.026) typ. 4.81 (0.189) iddg5322 25 0 p w ?c t 35 45 55 65 75 85 105 a 1.0 2.0 3.0 4.0 r j-a = 30 ?c/w d switching specifications (over operating temperature range and v cc =4.5v to 5.5v) symbol description min. units t acc display access time?write 210 ns t acc display access time?read 230 ns t acs address setup time to ce 10 ns t ce chip enable active time?write 140 ns t ce chip enable active time?read 160 ns t ach address hold time to ce 20 ns t cer chip enable recovery time 60 ns t ces chip enable active prior to rising edge?write 140 ns t ces chip enable active prior to rising edge?read 160 ns t ceh chip enable hold to rising edge of read/write signal 0 ns t w write active time 100 ns t wd data valid prior to rising edge of write signal 50 ns t dh data write time 20 ns t r chip enable active prior to valid data 160 ns t rd read active prior to valid data 95 ns t df read data float delay 10 ns t rc reset active time 300 ns oscillator, refresh, flash and self test characteristics parameters min. typ. max. units conditions clock i/o frequency 28 57.34 81.14 khz v cc =4.5 v to 5.5 v external clock frequency 25 ? 640 khz v cc =4.5 v to 5.5 v fm, digit multiplex frequency 125 256 362.5 hz v cc =4.5 v to 5.5 v blinking rate 0.98 2.0 2.83 hz ? clock i/o bus loading ? ? 2.40 pf ? clock out rise time ? ? 500 nsec v cc =4.5 v, v oh =2.4 v clock out fall time ? ? 500 nsec v cc =4.5 v, v oh =0.4 v
IPD2131, ipd2132, ipd2133 2006-04-04 5 write cycle timing diagram read cycle timing diagram t acc t wd t dh t w t ces t cer t ceh t acs t ach t acs a 0-a3 f l t ce c e w r d 0-d7 i nput pulse levels ?.6 v to 2.4 v t acc t rd t df t r t ces t cer t ceh t acs t ach t acs a 0-a3 f l t ce c e r d d 0-d7
2006-04-04 6 IPD2131, ipd2132, ipd2133 electrical characteristics at 25 c parameters limits conditions min. typ. max. units v cc 4.5 5.0 5.5 v ? i cc blank ? 0.5 1.0 ma v cc =5.0 v, v in =5.0 v i cc 12 dots/digit on (1) (2) ? 200 255 ma v cc =5.0 v, ?v? in all 8 digits i cc 20 dots/digit on (1) (2) ? 300 370 ma v cc =5.0 v, ?#? in all 8 digits i ilp (with pull-up) input leakage ?1.0 ?11 ?18 a v cc =5.0 v, v n =0 v to v cc ( wr , ce , fl , rst , rd , clksel ) i il (no pull-up) input leakage ?1.0 ? +1.0 a v cc =5.0 v, v in =0?5.0 v (clk, a0?a4, d0?d7) v ih input voltage high 2.0 ? v cc +0.3 v v cc =4.5 v to 5.5 v v il input voltage low gnd ?0.3 ? 0.8 v v cc =4.5 v to 5.5 v v ol (d0?d7), output voltage low ? ? 0.4 v v cc =4.5 v, i ol =1.6 ma v ol (clk), output voltage low ? ? 0.4 v v cc =4.5 v, i ol =40 a v oh output voltage high 2.4 ? ? v v cc =4.5 v, i oh =?40 a jc thermal resistance, junction to case ? 15 ? c/w ? recommended operating conditions ( t a = ? 55 c to + 100 c) parameter symbol min. max. units supply voltage v cc 4.5 5.5 v input voltage low v il ? 0.8 v input voltage high v ih 2.0 ? v output voltage low v ol ? 0.4 v output voltage high v oh 2.4 ? v
IPD2131, ipd2132, ipd2133 2006-04-04 7 pin description pin no. function description explanation 1 cls clock select selects an internal or external clock source. cls=1 the internal clock selected (master clock), cls=0 then external clock selected (slave operation). 2 clk clock i/o inputs or outputs the clock as determined by the cls pin. 3 wr write writes data into the display when wr =0 and ce =0. 4 ce chip enable enables the read/write access when low. 5 rst reset initializes the display; clears the character ram (20 hex), flash ram (00 hex), control word (00 hex) and resets the internal counters. udc address register and udc ram are unaffected. 6 rd read outputs data from the display when rd =0 and ce =0. 7 no pin ? ? 8 9 10 11 d0 data bus 8 bit bidirectional data bus. character ram and control word uses d7?d0, udc address register uses d3?d0, udc ram uses d4?d0, and flash ram uses d0. 12 d1 13 d2 14 d3 15 nc ? ? 16 v cc ? positive power supply. 17 gnd supply analog ground for the led drivers. 18 gnd logic digital ground for the logic circuitry. 19 d4 data bus 8 bit bidirectional data bus. character ram and control word uses d7-d0, udc address register uses d3-d0, udc ram uses d4-d0, and flash ram uses d0. 20 d5 21 d6 22 d7 23 no pin ? ? 24 25 26 27 fl flash accesses the flash ram. address inputs, a2?a0, select the digit address while data bit d0 sets (d0=1) or resets (d0=0) the flash bit. a4 and a3 are ignored. 28 a0 address inputs a4 and a3 select a section of the display?s memory. a2?a0 select specific locations in the different sections. if fl is low the flash ram is accessed regardless of the status of a4 and a3. 29 a1 30 a2 31 a3 32 a4
2006-04-04 8 IPD2131, ipd2132, ipd2133 character set notes: 1. upon power up, the device will initialize in a random state. 2. x=don?t care. cascading diagram cascading displays the display?s oscillator is designed to drive up to 16 other display?s with input loading of 15 pf each. the following are the general requirements for cascading 16 displays together: determine the correct address for each display. use ce from an address decoder to select the correct display. select one of the displays to provide the clock for the other displays. connect clksel to v cc for this display. tie clksel to ground on other displays. use rst to synchronize the blinking between the displays. idcs5086 ascii code d0 d1 d2 d3 hex d4 d5 d7 lll 0 1 h l l 2 lhl 3 lhh 4 lll 5 llh 6 lhl 7 lhh l l l l 0 1 l l h l 2 l l l h 3 l l h h 4 l h l l 5 l h h l 6 l h l h 7 l h h h 8 h l l l 9 h l h l a h l l h b h l h h c h h l l d h h h l e h h l h f h h h h d6 l l l l h h h h hx xx 8 udc 0 udc 1 udc 2 udc 3 udc 4 udc 5 udc 6 udc 7 udc 8 udc 9 udc 10 udc 11 udc 12 udc 14 udc 15 13 udc idcd5031 rd wr fl clk clk display cc v d0-d7 a0-a4 ce up to 14 more displays in between i/o sel ce display d0-d7 a0-a4 data i/o address decoder address address decode chip 1 to 14 a6 a7 a9 wr fl rst rst 0 15 rd rst rd wr fl clk sel clk i/o a8
IPD2131, ipd2132, ipd2133 2006-04-04 9 block diagram functional description the display's user interface is organized into five memory areas. they are accessed using the flash input, fl , and address lines, a3 and a4. all the listed rams and registers may be read or writ - ten through the data bus. see table ?memory selection? ( page 10 ). each input pin is described in pin definitions. rst can be used to initialize display operation upon power up or during normal operation. when activated, rst will clear the flash ram and control word register (00h) and reset the internal counter. all eight display memory locations will be set to 20h to show blanks in all digits. fl pin enables access to the flash ram . the flash ram will set (d0=1) or reset (d0=0) flashing of the character addressed by a0? a2. the 1 x 8 bit control word register is loaded with attribute data if a3=0. the control word logic decodes attribute data for proper imple - mentation. character rom is designed for 128 ascii characters. the rom is mask programmable for custom fonts. the clock source could either be the internal oscillator ( clksel =1) of the device or an external clock ( clksel =0) could be an input from another ipd213x display for synchronizing blink - ing for multiple displays. the display multiplexer controls the row drivers so no additional logic is required for a display system. the display has eight digits. each digit has 35 leds. idbd5064 osc 32 counter counter 7 8 digit display drivers counter 128 counter 3 decode ram character character ram d latch holding register decode word rom for display decode character (read/write) character decode register address udc bus row rom 4 64 4 ram 16 16 udc column latch master slave 5 25 5 and controls cursor display mux 25 word register control test self flash ram drivers column data five basic memory areas character ram stores either ascii (katakana) character data or an udc ram address flash ram 1 x 8 ram which stores flash data user-defined character ram (udc ram) stores dot pattern for custom characters user-defined address register (udc address register) provides address to udc ram when user is writing or reading custom character control word register enables adjustment of display brightness, flash individual charac - ters, blink, self test or clearing the display
IPD2131, ipd2132, ipd2133 2006-04-04 10 theory of operation the ipd213x display is designed to work with all major micropro - cessors. data entry is via an eight bit parallel bus. three bits of address route the data to the proper digit location in the ram. standard control signals like wr and ce allow the data to be writ - ten into the display. d0?d7 data bits are used for both character ram and control word data input. a3 acts as the mode selector. if a3=1, character ram is selected. then input data bit d7 will determine whether input data bits d0?d6 is ascii coded data (d7=0) or udc data (d7=1). see section on ?udc address regis - ter and udc ram? ( page 11 ). for normal operation fl pin should be held high. when fl is held low, flash ram is accessed to set character blinking. the seven bit ascii code is decoded by the character rom to generate column data. twenty columns worth of data is sent out each display cycle, and it takes fourteen display cycles to write into eight digits. the rows are multiplexed in two sets of seven rows each. the internal timing and control logic synchronizes the turning on of rows and presentation of column data to assure proper display operation. power up sequence upon power up the display will come on at random. thus the dis - play should be reset on power-up. reset will clear the flash ram, control word register and reset the internal counter. all the digits will show blanks and display brightness level will be 100%. the display must not be accessed until three clock pulses (110 s minimum using the internal clock) after the rising edge of the reset line. microprocessor interface the interface to a microprocessor is through the 8-bit data bus (d0?d7), the 4-bit address bus (a0?a3) and control lines fl , ce and wr . to write data (ascii/control word) into the display ce should be held low, address and data signals stable and wr should be brought low. the data is written on the low to high transition of wr . the control word is decoded by the control word decode logic. each code has a different function. the code for display brightness changes the duty cycle for the column drivers. the peak led cur - rent stays the same but the average led current diminishes depending on the intensity level. the character flash enable causes 2.0 hz coming out of the counter to be anded with the column drive signal to make the col - umn driver cycle at 2.0 hz. thus the character flashes at 2.0 hz. the display blink works the same way as the flash enable but causes all twenty column drivers to cycle at 2.0 hz thereby making all eight digits blink at 2.0 hz. the self test function of the ic consists of two internal routines which exercise major portions of the ic and illuminates all the leds. clear bit clears the character ram and writes a blank into the dis - play memory. it however does not clear the control word. ascii data or control word data can be written into the display at this point. for multiple display operation, clk i/o must be properly selected. clk i/o will output the internal clock if clk - sel =1, or will allow input from an external clock if clksel =0. memory selection fl a4 a3 section of memory a2?a0 data bits used 0xx flash ram character address d0 100 udc address register don?t care d3?d0 101 udc ram row address d4?d0 111 character ram character address d7?d0 11 0 control word register don?t care d7?d0
IPD2131, ipd2132, ipd2133 2006-04-04 11 character ram the character ram is selected when fl , a4 and a3 are set to 1,1,1 during a read or write cycle. the character ram is a 8 by 8 bit ram with each of the eight locations corresponding to a digit on the display. digit 0 is on the left side of the display and digit 7 is on the right side of the display. address lines, a2?a0 select the digit address with a2 being the most significant bit and a0 being the least significant bit. the two types of data stored in the character ram are the ascii coded data and the udc address data. the type of data stored in the character ram is determined by data bit, d7. if d7 is low, then ascii coded data is stored in data bits d6? d0. if d7 is high, then udc address data is stored in data bit d3? d0. the ascii coded data is a 7 bit code used to select one of 128 ascii characters permanently stored in the ascii rom. the udc address data is a 4 bit code used to select one of the udc characters in the udc ram. there are up to 16 characters available. see table ?character ram access logic? ( page 11 ). udc address register and udc ram the udc address register and udc ram allows the user to gen - erate and store up to 16 custom characters. each custom charac - ter is defined in 5 x 7 dot matrix pattern. it takes 8 write cycles to define a custom character, one cycle to load the udc address register and 7 cycles to define t he character. the contents of the udc address register will store the 4 bit address for one of the 16 udc ram locations. the udc ram is used to store the custom character. udc address register the udc address register is selected by setting fl =1, a4=0, a3=0. it is a 4 bit register and uses data bits, d3?d0 to store the 4 bit address code (d7?d4 are ignored). the address code selects one of 16 udc ram locations for custom character gen - eration. udc ram the udc ram is selected by setting fl =1, a4=0, a3=1. the ram is comprised of a 7 x 5 bit ram. as shown in table ?udc charac - ter map? ( page 12 ), address lines, a2-a0 select one of the 7 rows of the custom character. data bits, d4-d0 determine the 5 bits of column data in each row. each data bit corresponds to a led. if the data bit is high, then the led is on. if the data bit is low, the led is off. to create a character, each of the 7 rows of column data need to be defined. see tables ?udc address register and udc ram? ( page 11 ) and ?udc character map? ( page 12 ) for logic. flash ram the flash ram allows the display to flash one or more of the char - acters being displayed. the flash ram is accessed by setting fl low. a4 and a3 are ignored. the flash ram is a 8 x 1 bit ram with each bit corresponding to a digit address. digit 0 is on the left side of the display and digit 7 is on the right side of the display. address lines, a2?a0 select the digit address with a2 being the most signif - icant digit and a0 being the least significant digit. data bit, d0, sets and resets the flash bit for each digit. when d0 is high, the flash bit is set; and when d0 is low, it is reset. see table ?flash ram access logic? ( page 12 ). character ram access logic rst ce wr rd fl a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 1 1 1 1 character address for digits 0?7 0 7 bit ascii code for a write cycle 1 0 1 0 1 1 1 character address for digits 0?7 0 7 bit ascii code read during a read cycle 1 0 0 1 1 0 0 character address for digits 0?7 1 d3?d0=udc address for a write cycle 1 0 1 0 1 0 0 character address for digits 0?7 1 d3?d0=udc address for read data udc address register and udc character ram rst ce wr rd fl a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 1 1 0 0 not used for udc address register d3?d0=udc ram address code for write cycle udc address register 1 0 1 0 1 0 0 not used for udc address register d3?d0=udc ram address code for read cycle 1 0 0 1 1 0 1 a2?a0=character row address d4?d0=character column data for write cycle udc ram 1 0 1 0 1 0 1 a2?a0=character row address d4?d0=character column data read during a read cycle
IPD2131, ipd2132, ipd2133 2006-04-04 12 control word the control word is used to set up the attributes required by the user. it is addressed by setting fl =1, a4=1, a3=0. the control word is an 8 bit register and is accessed using data bits, d7?d0. see table ?control word access logic? ( page 12 ) and figure ?control word data definition? ( page 13 ) for the logic and attrib - uted control. the control word has 5 functions. they are bright - ness control, flashing character enable, blinking character enable, self test, and clear (flash and character rams only). brightness control control word bits, d2?d0, control the brightness of the display with a binary code of 000 being 100% brightness and 111 being display blank. see figure ?control word data definition? ( page 13 ) for brightness level versus binary code. the average i cc can be calculated by multiplying the 100% brightness level i cc value by the display?s brightness level. for example, a display set to 80% brightness with a 100% average i cc value of 200 ma will have an average i cc value of 200 ma x 80%=160 ma. flash function control word bit, d3, enables or disables the flash function. when d3 is 1, the flash function is enabled and any digit with its corresponding bit set in the flash ram will flash at approximately 2.0 hz. when using an external clock, the flash rate can be deter - mined by dividing the clock rate by 28,672. when d3 is 0, the flash function is disabled and the contents of the flash ram is ignored. for synchronized flashing on multiple displays, see the reset section ( page 13 ). blink function control word bit, d4, enables or disables the blink function. when d4 is 1, the blink function is enabled and all characters on the dis - play will blink at approximately 2.0 hz. the blink function will over - ride the flash function if both functions are enabled. when d4 is 0, the blink function is disabled. when using an external clock, the blink rate can be determined by dividing the clock rate by 28,672. for synchronized blinking on multiple displays, see the reset sec - tion ( page 13 ). self test control word bits, d6 and d5, are used for the self test function. when d6 is 1, the self test is init iated. results of the self test are stored in bit d5. control word bit, d5, is a read only bit. when d5 is 1, self test has passed. when d5 is 0, self test failed is indi - cated. the self test function of the ic consists of two internal rou - tines which exercise major portions of the ic and illuminates all of the leds. the first routine cycles the ascii decoder rom through all states and performs a check sum on the out-put. if the check sum is correct, d5 is set to a 1 (pass). the second routine provides a visual test of the leds. this is accomplished by writing checkered and inversed checkered pat - terns to the display. each pattern is displayed for approximately 2.0 sec. during the self test function the display must not be accessed. the time needed to execute the self test function is cal - culated by multiplying the clock time by 262,144 (typical time 4.6 sec.). at the end of the self test, the character ram is loaded with blanks; the control word register is set to zeroes except d5; the flash ram is cleared and the udc address regis - ter is set to all 1.0s. udc character map row data a2 a1 a0 row # column data c1 c2 c3 c4 c5 d4 d3 d2 d1 d0 0001 5 x 7 dot matrix pattern 0012 0103 0114 1005 1016 1107 flash ram access logic rst ce wr rd fl a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 1 0 x x flash ram address for digits 0?7 d0=flash data, 0=flash off and 1=flash on (write cycle) 1 0 1 0 0 x x flash ram address for digits 0?7 d0=flash data, 0=flash off and 1=flash on (read cycle) control word access logic rst ce wr rd fl a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 1 1 1 0 not used for control word control word data for a write cycle, see figure ?control word data definition? ( page 13 ) 1 0 1 0 1 1 0 not used for control word control word data for a read during a read cycle
IPD2131, ipd2132, ipd2133 2006-04-04 13 clear function (see figure ?control word data definition? ( page 13 ) and table ?clear function? ( page 13 )) control word bit, d7 clears the character ram to 20 hex and the flash ram to all zeroes. the rams are cleared within three clock cycles (110 s minimum, using the intern al clock) when d7 is set to 1. during the clear time the display must not be accessed. when the clear function is finished, bit 7 of the control word ram will be reset to a ?0?. control word data definition reset function the display should be reset on power up of the display ( rst =low). when the display is reset, the character ram, flash ram, and control word register are cleared. the display's internal counters are reset. reset cycle takes three clock cycles (110 s minimum using the internal clock). the dis - play must not be accessed during this time. to synchronize the flashing and blinking of multiple displays, it is necessary for the display to use a common clock source and reset all the displays at the same time to start the internal counters at the same place. while rst is low, the display must not be accessed by rd nor wr . key c clear function st self test bl blink function fl flash function br brightness control idcw5161 function blink self test function brightness control d7 d6 d5 d4 d3 d2 d1 d0 d1 d0 brightness control 100% brightness 00 80% brightness 01 1 53% brightness 0 1 40% brightness 1 disabled flash function d3 0 enabled 1 enabled (overrides flash function) disabled blink function d4 1 0 normal operation (x = bit ignored) r d5 x run self test, r = test result (1 = pass, 0 = fail) self test clear flash ram & character ram (character ram = 20 hex) normal operation 0 1 clear function d7 clear flash function d2 0 0 0 0 27% brightness blank display 11 1 1 1 0 10 1 0 0 20% brightness 13% brightness 0 0 1 d6 clear function ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 1 1 0 0 x x x x x x 0 1 x x x x x x x x x x x x x x clear disabled clear user ram, flash ram and display x=don?t care
2006-04-04 14 IPD2131, ipd2132, ipd2133 display cycle using built-in rom example display message ?showtime.? digit 0 is leftmost?closest to pin 1. logic levels: 0=low, 1=high, x=don?t care. rst ce wr rd fl a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation display 0 x 1 1 1 x x x x x x x x x x x x x reset. no read/write within 3 clock cycles all blank 1 0 0 1 1 1 0 x x x 0 0 x 0 0 0 1 1 53% brightness selected all blank 1 0 0 1 1 1 1 0 0 0 0 1 0 1 0 0 1 1 write ?s? to digit 0 s 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 0 write ?h? to digit 1 sh 1 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 1 1 write ?o? to digit 2 sho 1 0 0 1 1 1 1 0 1 1 0 1 0 1 0 1 1 1 write ?w? to digit 3 show 1 0 0 1 1 1 1 1 0 0 0 1 0 1 0 1 0 0 write ?t? to digit 4 showt 1 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 write ?i? to digit 5 showti 1 0 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 1 write ?m? to digit 6 showtim 1 0 0 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 write ?e? to digit 7 showtime displaying user defined character example load character ?a? into udc-5 and then display it in digit 2. logic levels: 0=low, 1=high, x=don?t care rst ce wr rd fl a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation display 0 x 1 1 1 x x x x x x x x x x x x x reset. no read/write within 3 clock cycles all blank 1 0 0 1 1 0 0 x x x x x x x 0 1 0 1 select udc-5 all blank 1 0 0 1 1 0 1 0 0 0 x x x 0 1 1 1 0 write into row 1 of udc-5 all blank 1 0 0 1 1 0 1 0 0 1 x x x 1 0 0 0 1 write into row 2 of udc-5 all blank 1 0 0 1 1 0 1 0 1 0 x x x 1 0 0 0 1 write into row 3 of udc-5 all blank 1 0 0 1 1 0 1 0 1 1 x x x 1 1 1 1 1 write into row 4 of udc-5 all blank 1 0 0 1 1 0 1 1 0 0 x x x 1 0 0 0 1 write into row 5 of udc-5 all blank 1 0 0 1 1 0 1 1 0 1 x x x 1 0 0 0 1 write into row 6 of udc-5 all blank 1 0 0 1 1 0 1 1 1 0 x x x 1 0 0 0 1 write into row 7 of udc-5 all blank 1 0 0 1 1 1 1 0 1 0 1 x x x 0 1 0 1 write udc-5 into digit 2 (digit 2) a
IPD2131, ipd2132, ipd2133 2006-04-04 15 electrical and mechanical considerations voltage transient suppression for best results power the display and the components that inter - face with the display to avoid logic inputs higher than v cc . addi - tionally, the leds may cause transients in the power supply line while they change display states. the common practice is to place a parallel combination of a 0.01 f and a 22 f capacitor between v cc and gnd for all display packages. esd protection the input protection structure of the IPD2131x provides significant protection against esd damage. it is capable of withstanding dis - charges greater than 4.0 kv. take all the standard precautions nor - mal for cmos components. these include properly grounding personnel, tools, tables, and transport carriers that come in con - tact with unshielded parts. if these conditions are not, or cannot be met, keep the leads of the device shorted together or the parts in anti-static packaging. soldering considerations the ipd213x can be hand soldered with sn63 solder using a grounded iron set to 260 c. wave soldering is also possible. use water soluble organic acid flux or resin based rma flux. a wave temperature of 245 c 5 c with a dwell between 1.5 sec. to 3.0 sec. can be used. exposure to the wave should not exceed temperatures above 260c for five seconds at 1.59 mm (0.063") below the seating plane. the packages should not be immersed in the wave. post solder cleaning procedures the least offensive cleaning solution is hot d.i. water (60 c) for less than 15 minutes. addition of mild saponifiers is acceptable. do not use commercial dishwasher detergents. for faster cleaning, solvents may be used. suggested solvents include genesolv de-15, genesolv di-15, and genesolv des. an alternative to soldering and cleaning the display modules is to use sockets. multiple display assemblies are best handled by longer sip sockets or dip sockets when available for uniform package alignment. socket manufacturers are aries electronics, inc., frenchtown, nj; garry manu facturing, new brunswick, nj; robinson-nugent, new albany, in; and samtec electronic hard - ward, new albany, in. for further information refer to appnote 22 at www.osram-os.com optical considerations the 4.85 mm (0.200") high character of the ipd213x gives read - ability up to eight feet. proper filter selection enhances readability over this distance. using filters emphasizes the contrast ratio between a lit led and the character background. this will increase the discrimination of different characters. the only limitation is cost. take into consider - ation the ambient lighting environment for the best cost/benefit ratio for filters. incandescent (with almost no green) or fluorescent (with almost no red) lights do not have the flat sp ectral response of sunlight. plas - tic band-pass filters are an inexpensive and effective way to strengthen contrast ratios. the hi gh efficiency red displays should be matched with a long wavelength pass filter in the 570 nm to 590 nm range. the ipd2133 should be matched with a yel - low-green band-pass filter that peaks at 565 nm. for displays of multiple colors, neutral density gr ey filters offer the best compro - mise. additional contrast enhancement is gained by shading the dis - plays. plastic band-pass filters with built-in louvers offer the next step up in contrast improvement. plastic filters can be improved further with anti-reflective coatings to reduce glare. the trade-off is fuzzy characters. mounting the filters close to the display reduces this effect. take care not to overheat the plastic filter by allowing for proper air flow. optimal filter enhancements are gained by using circular polarized, anti-reflective, band-pass filters. the circular polarizing further enhances contrast by reducing the light that travels through the filter and reflects back off the display to less than 1%. several filter manufacturers supply quality filter materials. some of them are: panelgraphic corporation, w. caldwell, nj; sgl homa - lite, wilmington, de; 3m company, visual products division, st. paul, mn; polaroid corporation, polarizer division, cambridge, ma; marks polarized corporation, deer park, ny, hoya optics, inc., fremont, ca. one last note on mounting filters: recessing displays and bezel assemblies is an inexpensive way to provide a shading effect in overhead lighting situations. several bezel manufacturers are: r.m.f. products, batavia, il; no bex components, griffith plastic corp., burlingame, ca; photo chemical products of california, santa monica, ca; i.e.e.-atlas, van nuys, ca. rohs compliance the ipd2132, IPD2131, ipd2133 intelligent displays tm are her - metically sealed displays using a ceramic and glass construction. these components are not lead (pb) free but are rohs compliant based on the rohs compliance directive's annex, paragraphs 5 and 7. these exemptions allow for lead (pb) in glass and ceramic electronic components. refer to the following excerpts from the rohs compliance directive annex: applications of lead, mercury, cadmium and hexavalent chromium, which are exempted from the requirements of article 4(1) 5. lead in glass of cathode ray tubes, electronic components and fluorescent tubes. 7. lead in electronic ceramic parts (e.g. piezoelectronic devices).
2006-04-04 16 IPD2131, ipd2132, ipd2133 p ublished by osram opto semiconductors gmbh wernerwerkstrasse 2, d-93049 regensburg www.osram-os.com ? all rights reserved. attention please! the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for informati on on the types in question please contact our sales organization. if printed or downloaded, please find the latest version in the internet. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1) may only be used in life-support devices or systems 2) with the express written approval of osram os. 1) a critical component is a component used in a life-support devi ce or system whose failure can reasonably be expected to cause t he failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system. 2) life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and susta in human life. if they fail, it is reasonable to assume that the health and the life of the user may be endangered. revision history: 2006-04-04 previous version: 2004-11-11 page subjects (major changes since last revision) date of change all rohs compliant - by exemption 2006-03-03

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